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ymf715e opl3-sa3 opl3 single-chip audio system 3 may 21, 1998 ymf715e catalog catalog no.:lsi-4mf715e20 may 21, 1998 outline YMF715E-S (opl3-sa3) is a single audio chip that integrates opl3 and its dac, 16bit sigma-delta codec, mpu401 midi interface, joystick port, and a 3d enhanced controller including all the analog components which is suitable for multi-media application. this lsi is fully compliant with plug and play isa 1.0a, and supports all the necessary features, i.e. 16bit address decode, more irqs and dmas in compliance with pc98. this lsi also supports the expandability, i.e. zoomed video, modem and cd- rom interface in a plug and play manner, and power management (power down, power save, partial power down, and suspend/resume) that is indispensable with power-conscious application. features ? built-in opl3 (fm-synthesizer) ? supports sound blaster game compatibility ? supports windows sound system compatibility ? supports plug & play isa 1.0a compatibility ? full duplex operation ? built-in mpu401 compatible midi i/o port ? built-in joystick port ? codecs dac : s/n=82db (min.) ? built-in the 3d enhanced controller including all the analog components ? supports multi-purpose pin function (support 16-bit address decode, dac interface for opl4-ml/ml2, zoomed video port, eeprom interface, modem interface, ide cd-rom interface) ? hardware and software master volume control ? supports monaural input ? 24 ma ttl bus drive capability ? supports power management(power down, power save, partial power down, and suspend/resume) ? +5v/ +3.3v power supply for digital, 5v power supply for analog. ? 100 pin sqfp package (YMF715E-S) yamaha corporation general midi logo is a trademark of association of musical electronics industry (amei), and indicates gm system level 1 compliant. ymersion logo is a trademark of yamaha corporation. xglite logo is a trademark of yamaha corporation.
ymf715e may 21, 1998 -2- pin configuration YMF715E-S 100 pin sqfp top view 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 sbfltr sbfltl synshl synshr trecr trecl aux2l aux2r mic min vrefo vrefi avss avdd linel liner aux1l aux1r outl outr vocil vocir vocor vocol adfltl adfltr dvss sel0 sel1 sel2 mp0 mp1 mp2 mp3 mp4 mp5 mp6 mp7 mp8 mp9 dvdd / volup / voldw a0 a1 a2 x33o x33i x24o x24i avss avdd gp0 gp1 gp2 gp3 gp4 gp5 gp6 gp7 dvss reset /iow /ior dvdd aen a11 a10 a9 irq3 irq5 irq7 irq9 irq10 irq11 drq0 /dack0 drq1 /dack1 drq3 /dack3 d0 d1 d2 d3 dvdd dvss d4 d5 d6 d7 a8 a7 a6 a5 a4 a3 dvss rxd txd
ymf715e may 21, 1998 -3- pin description isa bus interface: 36 p ins name p ins i/o t yp e size function d7-0 8 i/o ttl 24ma data bus a11-0 12 i ttl - address bus aen 1 i ttl - address bus enable /iow 1 i schmitt - write enable /ior 1 i schmitt - read enable reset 1 i schmitt - reset ir q 3,5,7,9,10,11 6 t ttl 12ma interru p t re q uest dr q 0, 1, 3 3 t ttl 12ma dma re q uest /dack0, 1, 3 3 i ttl - dma acknowled g e analo g in p ut & out p ut : 24 p ins name p ins i/o t yp e size function outl 1 o - - left mixed analo g out p ut outr 1 o - - ri g ht mixed analo g out p ut vrefi 1 i - - volta g e reference in p ut vrefo 1 o - - volta g e reference out p ut aux1l 1 i - - left aux1 in p ut aux1r 1 i - - ri g ht aux1 in p ut aux2l 1 i - - left aux2 in p ut aux2r 1 i - - ri g ht aux2 in p ut linel 1 i - - left line in p ut liner 1 i - - ri g ht line in p ut mic 1 i - - mic in p ut min 1 i - - monaural in p ut trecl 1 - - - left treble ca p acitor trecr 1 - - - ri g ht treble ca p acitor sbfltl 1 - - - left sbdac filter sbfltr 1 - - - ri g ht sbdac filter synshl 1 - - - left syndac sam p le / hold ca p acitor synshr 1 - - - ri g ht syndac sam p le / hold ca p acitor adfltl 1 - - - left in p ut filter adfltr 1 - - - ri g ht in p ut filter vocol 1 o - - left voice out p ut vocor 1 o - - ri g ht voice out p ut vocil 1 i - - left voice in p ut vocir 1 i - - ri g ht voice in p ut
ymf715e may 21, 1998 -4- multi- p ur p ose p ins : 13 p ins name p ins i/o t yp e size function sel2-0 3 i+ cmos - refer to multi-purpose pins section mp9-0 10 i+/o ttl 2ma refer to multi-purpose pins section others : 27 p ins name p ins i/o t yp e size function gp3-0 4 ia - - game port gp7-4 4 i+ schmitt - game port rxd 1 i+ schmitt - midi data receive txd 1 o ttl 4ma midi data transfer /volup 1 i+ schmitt - hardware volume (up) /voldw 1 i+ schmitt - hardware volume (down) x33i 1 i cmos - 33.8688 mhz x33o 1 o cmos 2ma 33.8688 mhz x24i 1 i cmos - 24.576 mhz x24o 1 o cmos 2ma 24.576 mhz avdd 2 - - - analo g power su pp l y (p ut on +5.0v ) dvdd 3 - - - di g ital power su pp l y (p ut on +5.0 v or +3.3v ) avss 2 - - - analo g gnd dvss 4 - - - di g ital gnd total : 100 pins note : i+: input pin with pull up resistor t: ttl-tri-state output pin schmitt: ttl-schm itt input pin
ymf715e may 21, 1998 -5- block diagram / voldw synth. d/a mux 512 byte sram reset tim. generator vref fifo capture data format cpu interface input gain d/a d/a loop attn. opl3 fm synthesizer control register i) 16bit decode iii) zv port v) modem i/f ii) eeprom i/f iv) opl4-ml i/f vi) cdrom i/f multi-purpose multi p lex joy stick logic port mpu401 uart with fifo sb pro mixer register sound blaster pro command interpreter ml/i 2 s s/p sb d/a 8step mux mux 16step 16step a/d a/d fifo play data format +20db mux 32step 32step 32step 3d enhanced control 64step 16step 16step master 64step 64step 32step aux2 line mic aux1 loop mono_loop d[7-0] a[11-0] aen /iow /ior drq[0,1,3] irq[11,10,9 7,5,3] sbfltl/r aux2r aux2l min trecl/r / volup, outr outl vocil vocir vocor vocol linel liner aux1l aux1r mic avdd avss adfltl adfltr vrefi vrefo dvss dvdd x24o x24i x33o x33i sel[2-0] mp[9-0] gp[3-0] gp[7-4] synshl/r rxd txd isa bus interface plug and pla y i/o address dma channel irq channel configuration register decode logic 8 12 3 3 6 310 442 2 2 2 /dack[0,1,3]
ymf715e may 21, 1998 -6- function overview 1. multi-purpose pin 1-1. multi-purpose function opl3-sa3 can support the various functions listed below by programming sel2-0 pins. a. 16-bit address decode b. eeprom interface c. zoomed video port d. cpu and dac interface for opl4-ml/ml2 e. modem interface f. ide cd-rom interface following table shows what combinations of the above functions are available for each sel2-0 pins. sel 16bit dec. eeprom zv port opl4-ml/ml2 modem cdrom remark 0 - - - - - - test mode 1 o (*1) o - o (*2) o o (*1) s/c,c/c(add-in) 2 o o - o (*3) o - s/c (add-in) 3 o (*4) o - o - - s/c (add-in) 4 o (*4) - o o - - note pc 5 o - o o (*3) o - note pc 6 - - - - - - reserved 7 o - - o - - m/b, note pc where, s/c : sound card c/c : combo card (sound and modem) m/b : desktop mother board sel=0 sel=1 sel=2 sel=3 sel=4 sel=5 sel=6 sel=7 sel0 pin01010101 sel1 pin00110011 sel2 pin00001111 notice *1 : external pal is needed. *2 : external wavetable synthesizer (ex.opl4-ml/ml2) is mixed as analog signal using external dac. *3 : clock module (ex.mk1420) is used to generate the clock for opl4-ml/ml2 and it will be mixed analog signal by having an additional dac. *4 : external ttls (ex.ls138) is needed. see section 1-2 and 1-3 for implementation detail.
ymf715e may 21, 1998 -7- 1-2. pin description sel=0 sel=1 sel=2 sel=3 sel=4 sel=5 sel=6 sel=7 mp0 - /mcs /mcs /exten /exten /mcs - /exten mp1 - mirq mirq /syncs /syncs mirq - /syncs mp2 - romclk romclk romclk bclk_zv a12 - a12 mp3 - romcs romcs romcs lrck_zv a13 - a13 mp4 - romdi romdi romdi sin_zv a14 - a14 mp5 - romdo romdo romdo /xrst a15 - a15 mp6 - /cdcs0 a12 bclk_ml bclk_ml bclk_zv - bclk_ml mp7 - /cdcs1 a13 lrck_ml lrck_ml lrck_zv - lrck_ml mp8 - cdirq a14 sin_ml sin_ml sin_zv - sin_ml mp9 - clko a15 clko clko /xrst - clko note : do not select sel=0 and sel=6. sel=0 ; test mode sel=6 ; reserved mutil- p ur p ose p ins: name i/o function /mcs o chi p select out p ut for modem chi p ( com ) mir q i+ interru p t re q uest in p ut for modem ( com ) romclk o serial data clock out p ut for external eeprom romcs o chi p select out p ut for external eeprom romdi i+ serial data in p ut for external eeprom romdo o serial data out p ut for external eeprom /cdcs0 o chi p select out p ut for ide cd-rom ( /cs1fx ) /cdcs1 o chi p select out p ut for ide cd-rom ( /cs3fx ) cdir q i+ interru p t re q uest in p ut for ide cd-rom a12 - 15 i address bus for isa-bus /exten i+ enable opl4-ml/ml2 interface /syncs o chi p select out p ut for opl4-ml/ml2 bclk_ml i+ bit clock in p ut for opl4-ml/ml2 lrck_ml i+ l/r clock in p ut for opl4-ml/ml2 sin_ml i+ serial data in p ut for opl4-ml/ml2 clko o master clock out p ut ( 33.8688mhz ) bclk_zv i+ bit clock in p ut for zoomed video p ort ( i 2 s ) lrck_zv i+ l/r clock in p ut for zoomed video p ort ( i 2 s ) sin_zv i+ serial data in p ut for zoomed video p ort ( i 2 s ) /xrst o inverted reset out p ut
ymf715e may 21, 1998 -8- 1-3. system block diagram (1) sel=1 (sound card and combo card add-in) 1. external pal(16v8 etc.) (i) connect the signal aen* generated by decoding sa15-12 and aen to the aen of opl3- sa3. (ii) generate the /g(enable) signal for data bus buffer (ls245) by decoding the /cdcs1-0 and sa2-0. (iii) generate the /reset signal from resetdrv. modem i/f sd15-8 / enh sa2-0 sa15-12 / reset aen 245 ide cd-rom i/f 16v8 resetdrv 245 YMF715E-S (opl3-sa3) eeprom yac516 opl4-ml/ml2 / enl cdirq aen* /cdcs1 /cdcs0 / iow,/ior reset aux2l aux2r xi rxd bco clko do2 lro reset /iow,/ior a11-0 sa11-0 d7-0 sd7-0 sd7-0 mp8 aen mp7 mp6 mp0 mp1 / mcs mirq mp3 mp2 txd mp9 mp5 txd clko mp4 romdo romdi romcs romcl k }
ymf715e may 21, 1998 -9- 2. master clock both 33.8688mhz and 24.576mhz are used or 14.31818mhz and clock module (ex.mk1420 by micro clock) are used. 3. opl4-ml/ml2 the external dac (yac516) is necessary for wavetable upgrade. (2) sel=2 (sound card and combo card for add-in) 1. opl4-ml/ml2 the external dac (yac516) and the clock module (ex.mk1420 by micro clock) are necessary for wavetable upgrade. 2. mk1420 the mk1420 is the clock module that generates all clocks necessary for this chipset . it is by micro clock and its package is sop8. aen resetdrv YMF715E-S (opl3-sa3) eeprom mk1420 yac516 opl4-ml/ml2 / iow,/ior reset aux2l aux2r xi rxd bco clko do2 lro reset /iow,/ior a11-0 sa11-0 14.31818mhz d7-0 x33i x24i sd7-0 mp0 mp1 / mcs mirq mp3 mp2 txd mp5 txd 33.8688mhz 24.576mhz mp4 romdo romdi romcs romcl k } modem i/f mp9-6 aen sa15-12
ymf715e may 21, 1998 -10- (3) sel=3 (sound card for add-in) 1. 16bit address decode the signal aen* generated by decoding sa15-12 and aen needs to be connected to the aen of opl3-sa3. aen resetdrv YMF715E-S (opl3-sa3) eeprom 138 opl4- ml/ml2 / iow,/ior reset mp6 mp7 mp8 rxd do2 bco lro d7-0 /iow /ior a2-0 dbdir reset /iow,/ior sa2-0 /iow,/ior a11-0 sa11-0 d7-0 sd7-0 sd7-0 mp3 mp2 txd mp5 txd mp4 romdo romdi romcs romcl k aen* aen sa15-12 xii mp9 clko /oplcs mp0 mp1 /exten /syncs bclk_ml lrck_ml sin_ml 245
ymf715e may 21, 1998 -11- (4) sel=4 (for notebook pc) 1. 16bit address decode the signal aen* generated by decoding sa15-12 and aen needs to be connected to the aen of opl3-sa3. 2. zv port and opl4-ml/ml2 i/f zv port is supported by using the internal dac of opl3-sa3 that is originally dedicated for the use of internal opl3. (i) either opl4-ml/ml2 or zv port is active at a time and simultaneous use is not possible. (ii) which function the internal dac is used for is determined by the sa3 control register, index 02h, vze bit. aen resetdrv YMF715E-S (opl3-sa3) 138 opl4- ml/ml2 / iow,/ior reset mp6 mp7 mp8 rxd do2 bco lro d7-0 /iow /ior a2-0 dbdir reset /iow,/ior sa2-0 /iow,/ior a11-0 sa11-0 d7-0 sd7-0 sd7-0 txd txd aen* aen sa15-12 xii mp9 clko /oplcs mp0 mp1 /exten /syncs bclk_ml lrck_ml sin_ml 245 mp2 mp3 mp4 mp5 sin_zv / xrst lrck_zv bclk_zv } zv port peripheral equipment
ymf715e may 21, 1998 -12- (5) sel=5 (for notebook pc) 1. internal dac the internal opl3 and the zv port shares the internal dac, which is very similar to the case mentioned the previous section. (i) either internal opl3 or zv port is active at a time and simultaneous use is not possible. (ii) which function the internal dac is used for is determined by the sa3 control register, index 02h, vze bit. 2. opl4-ml/ml2 the external dac (yac516) and the clock module (ex.mk1420 by micro clock) are necessary for wave table upgrade. aen resetdrv YMF715E-S (opl3-sa3) / iow,/ior reset mp6 mp7 mp8 /iow,/ior a11-0 mp5-2 sa11-0 d7-0 sd7-0 aen sa15-12 bclk_zv lrck_zv sin_zv mp0 mp1 / xrst } zv port peripheral equipment mp9 / mcs mirq } modem i/f yac516 opl4-ml/ml2 aux2l aux2r rxd bco clko do2 lro reset txd txd mk1420 xi 14.31818mhz x33i x24i 33.8688mhz 24.576mhz
ymf715e may 21, 1998 -13- (6) sel=7 (for notebook pc, desktop pc) aen resetdrv YMF715E-S (opl3-sa3) / iow,/ior reset mp6 mp7 mp8 /iow,/ior a11-0 mp5-2 sa11-0 d7-0 sd7-0 aen sa15-12 bclk_ml lrck_ml sin_ml d7-0 /iow /ior a2-0 dbdir /iow,/ior sa2-0 sd7-0 xii mp9 clko /oplcs mp0 opl4- ml/ml2 mp1 rxd /exten do2 /syncs bco lro reset txd txd 245
ymf715e may 21, 1998 -14- 2. isa interface opl3-sa3 supports isa plug and play (pnp) that frees the users from configuring the i/o address, irq and dma channel. those system resources are set automatically by the system. however even when used in non pnp system, the configuration can be changed with software. 2-1. pnp auto-configuration mode opl3-sa3 has the following i/o port to support the plug and play isa. address port: 279h write data port: a79h relocatable read data port: 203h - 03ffh the following four logical devices are supported by opl3-sa3. logical device no. 0 sound blaster compatible playback system (sb base) 16-bit codec (wss base) mpu401 (mpu base) opl3 (adlib base) opl3-sa3 control register (ctrl base) logical device no. 1 joy stick logical device no. 2 (optional) modem (com port) logical device no. 3 (optional) ide cd-rom interface
ymf715e may 21, 1998 -15- 2-2. pnp isa configuration register opl3-sa3 has the following registers defined in the pnp isa software. ldn=3, cdrom ldn=1, jo y stick ldn=0, sa3 sound system card control 0x75 0x30 0x22 0x00 ldn=2, modem listed below is the register map of card control register and logical device registers. for the detailed description of each register, please refer to the plug and play isa specification 1.0a card control registers index r/w d7 d6 d5 d4 d3 d2 d1 d0 00h w set rd_data 01h r serial isolation 02h w config control 03h w wake [csn] 04h r resource data 05h r status 06h r/w card select number 07h r/w logical device number 20h w resource data write 21h w ikd rdwe rdwe : resource data write enable setting 1 to this bit means the host can download the resources data to eeprom and internal sram via 20h. ikd : initiation key disable setting 1 to this bit means opl3-sa3 should not detect the initiation key in the wait for key state.
ymf715e may 21, 1998 -16- logical device number = 0 : sa3 sound system 30h r/w activate 60h r/w i/o port base address[15..8], descriptor 0 (sb base) 61h r/w i/o port base address[7..0], descriptor 0 (sb base) 62h r/w i/o port base address[15..8], descriptor 1 (wss base) 63h r/w i/o port base address[7..0], descriptor 1 (wss base) 64h r/w i/o port base address[15..8], descriptor 2 (adlib base) 65h r/w i/o port base address[7..0], descriptor 2 (adlib base) 66h r/w i/o port base address[15..8], descriptor 3 (mpu base) 67h r/w i/o port base address[7..0], descriptor 3 (mpu base) 68h r/w i/o port base address[15..8], descriptor 4 (ctrl base) 69h r/w i/o port base address[7..0], descriptor 4 (ctrl base) 70h r/w interrupt request level select 0 (for irq-a) 71h r interrupt request type select 0 (for irq-a) 72h r/w interrupt request level select 1 (for irq-b) 73h r interrupt request type select 1 (for irq-b) 74h r/w dma channel select 0 (for dma-a) 75h r/w dma channel select 1 (for dma-b) logical device number = 1 : joystick 30h r/w activate 60h r/w i/o port base address[15..8] 61h r/w i/o port base address[7..0] logical device number = 2 : modem (optional) 30h r/w activate 60h r/w i/o port base address[15..8] 61h r/w i/o port base address[7..0] 70h r/w interrupt request level select 71h r interrupt request type select
ymf715e may 21, 1998 -17- logical device number = 3 : cd-rom (optional) 30h r/w activate 60h r/w i/o port base address [15..8], descriptor 0 (/cdcs0) 61h r/w i/o port base address [7..0], descriptor 0 (/cdcs0) 62h r/w i/o port base address [15..8], descriptor 1 (/cdcs1) 63h r/w i/o port base address [7..0], descriptor 1 (/cdcs1) 70h r/w interrupt request level select 71h r interrupt request type select 2-3. recommended resource data the recommended resource data is the followings. (1) ldn=0:sa3 sound system i/o (sb base): 16bit address decode index best acceptable1 acceptable2 acceptable3 i/o 220h 240h 220-280h <- length 16 16 16 <- alignment - - 16 <- i/o (wss base): 16bit address decode index best acceptable1 acceptable2 acceptable3 i/o 530h e80h 530-f48h <- length 8 8 8 <- alignment - - 8 <- i/o (adlib base): 16bit address decode index best acceptable1 acceptable2 acceptable3 i/o 388h <- 388-3f8h <- length 8 <- 8 <- alignment - - 8 <- i/o (mpu base): 16bit address decode index best acceptable1 acceptable2 acceptable3 i/o 330h 300h 300-334h <- length 2 2 2 <- alignment - - 2 <- i/o (ctrl base): 16bit address decode index best acceptable1 acceptable2 acceptable3 i/o 370h 100-ffeh <- <- length 2 2 <- <- alignment - 2 <- <-
ymf715e may 21, 1998 -18- irq-a: high-active, edge-sense index best acceptable1 acceptable2 acceptable3 irq 10 7,9,10,11 5,7,9,10,11 <- irq-b: high-active, edge-sense index best acceptable1 acceptable2 acceptable3 irq 5 5,7 5,7,9,10,11 <- dma-a: 8bit, count by byte, type-a, b, f index best acceptable1 acceptable2 acceptable3 dma 0 0,1,3 0,1,3 <- dma-b: 8bit, count by byte, type-a, b, f index best acceptable1 acceptable2 acceptable3 dma 1 0,1,3 0,1,3 <- (2) ldn=1:joystick i/o (game port): 16bit address decode index best acceptable1 acceptable2 acceptable3 i/o 201h 202h 203h 204-20fh length 1 1 1 1 alignment - - - 1 (3) ldn=2:modem i/o (/mcs): 16bit address decode index best acceptable1 acceptable2 acceptable3 i/o 2f8h 100-ff8h <- <- length 8 8 <- <- alignment - 8 - - irq: high-active, edge-sense index best acceptable1 acceptable2 acceptable3 irq 3 <- <- <-
ymf715e may 21, 1998 -19- (4) ldn=3:cd-rom i/o (/cdcs0): 16bit address decode index best acceptable1 acceptable2 acceptable3 i/o 1e8h 100-1f8h <- <- length 8 8 <- <- alignment - 8 <- <- i/o (/cdcs1): 16bit address decode index best acceptable1 acceptable2 acceptable3 i/o 3eeh 306-3f6h <- <- length 1 1 <- <- alignment - 8 <- <- irq: high-active, edge-sense index best acceptable1 acceptable2 acceptable3 irq 11 3,5,7,9,10,11 <- <- 2-4. manual configuration mode when opl3-sa3 is in the wait for key state, it can be changed to the manual configuration mode by sending the following yamaha key to address_port. the manual configuration mode is used for downloading the resource data to eeprom and internal sram, setting up the opl3-sa3 without pnp protocol. yamaha key: b1h, d8h, 6ch, 36h, 9bh, 4dh, a6h, d3h, 69h, b4h, 5ah, adh, d6h, ebh, 75h, bah, ddh, eeh, f7h, 7bh, 3dh, 9eh, cfh, 67h, 33h, 19h, 8ch, 46h, a3h, 51h, a8h, 54h in the manual configuration mode, pnp registers can be accessed by the host without pnp protocol. right after opl3-sa3 is switched to the manual configuration mode, set 81h in csn register automatically to put opl3-sa3 in sleep state. and when 81h is written to wake [csn], it becomes possible to access to configuration register of each logical device from the host. to return from the manual configuration mode to pnp auto-configuration mode, the wait for key command should be sent. note : the manual configuration mode can not be used in the system with more than one opl3-sa3s card installed in the isa slot.
ymf715e may 21, 1998 -20- 3. download resource data when opl3-sa3 is in the configuration state, the host can download the resources data to eeprom and internal sram via 20h: resource data write. to switch opl3-sa3 into configuration mode, there are two methods. first method is to use the normal pnp protocol. after csn was assigned for all isa cards by pnp soft- ware, get csn from cm (configuration manager) and write the csn to wake [csn], then opl3-sa3 switches into configuration state. second method is to use the yamaha key sequence which is described in the manual configuration mode section. after opl3-sa3 detects yamaha key, opl3-sa3 switches into the sleep state. writing ? 81h ? to wake [csn] register changes opl3-sa3 into configuration state. after opl3-sa3 switches into the configuration state, download the resource data to eeprom and internal sram by using following sequence. 1. write 01h(rdwe bit = 1) to 21h: resource data write enable register to reset internal address counter and to enable downloading the data. 2. write resource data to 20h: resource data write register until downloading data is completed. 3. write 00h to 21h: resource data write enable register to disable downloading . 4. external eeprom the resource data information of opl3-sa3 used for pnp auto configuration is stored in external eeprom. and either 256 x 16-bit eeprom or 128 x 16-bit eeprom, such as 93c55, 93c56, 93c65, 93c66 should be used. 5. hardware volume control 5-1. hardware volume up/down/mute control two digital input pins; /volup and /voldw can control the master volume of opl3-sa3. when /volup is low level, register value of master volume is decremented(-1). when the value reaches to 00h(max.0db), the input signal will not be effective. when /voldw is low level, register value of master volume is incremented(+1). when the value reaches to 0fh(min.-30db), the input signal will not be effective. when both of the /volup and /voldw are low level simultaneously, volume is muted. when either /volup or /voldw is low level, the previous value becomes effective, and volume is no mute. 5-2. hardware volume interrupt if configured ven(hardware volume enable)=1, sa3 control register, index 0ah, d7 bit, when one of the hardware volume control pins /volup or /voldw is asserted or when both are asserted to request mute, interrupt will be posted in the interrupt channel specified in sa3 control register, index 17h, irq-a mv or irq-b mv bit. note that when the muting is in effect, the subsequent mute requests which does not change any register contents will generate interrrupts. the ignored up/down requests (up requests with 0db volume attn., down requests with -30db) will not generate interrupts. this bit is cleared upon hosts reading the master volume lch register, sa3 control register, index 07h.
ymf715e may 21, 1998 -21- 6. dac interface opl3-sa3 supports two types of dac interface format. one is the conventional dac interface format (very common for the consumer audio product) for opl4-ml/ml2. another is the i 2 s format for zoomed video port. these two types of the formats are shown in the following fig.6-1, 2. 7. 3d enhanced control opl3-sa3 integrates the 3d enhanced controller including all the analog components in conventional systems. wide, bass, and treble controls are available via sa3 control register, index 14h, 15h, 16h. one of the four 3d enhancement modes can be selected according to the frequency response of the speaker. these are controlled by sa3 control register, index 02h d5, d4 bit (ymode1-0). ymode1 ymode0 3d enhancement mode target speaker speaker size 0 0 desktop mode standard speaker 5 ~ 12cm 0 1 notebook pc mode (1) small speaker 3cm 1 0 notebook pc mode (2) smaller speaker 1.5cm 1 1 hi-fi mode hi-fi speaker 16 ~ 38cm following diagram(fig.7-1) shows the 3d enhanced controller sub-system. 0 10 1 2 3 4 5 6 7 8 9 10 11 15 14 13 12 0 1 2 3 4 5 6 7 8 9 10 11 15 14 13 12 bclk sin lrck fig.6-1 conventional dac interface format for opl4-ml/ml2 left channel ri g ht channel 0 1 2 3 4 5 6 7 8 9 10 11 15 ri g ht channel left channel 14 13 12 0 1 2 3 4 5 6 7 8 9 10 11 15 14 13 12 bclk sin lrck fig.6-2 i 2 s format for zoomed video port fig.7-1 3d enhanced control block diagram yamaha 3d enhanced controller (analog components) { } { mic,liner, aux1r,aux2r, min,sbr,wss_pbr rch lch to hardware volume control mic,linel, aux1l,aux2l, min,sbl,wss_pbl
ymf715e may 21, 1998 -22- 8. power management following 4 functionalities are provided for apm(advanced power management) compliance. (1) partial power down mode (2) power save mode (3) global power down mode (4) suspend/resume mode fig.8-1 power management plug and play 1bit d/a scf wss- recording vref mixing circuit 3d enhanced controller (wide stereo) 1bit a/d scf wss-playback fm dac fm(opl3) sb dac clock- out joy- stick mpu 401 sound blaster clock generator : global power down : power save 1,2 : partial power down (digital) : 8 digital blocks can be disabled independently. : partial power down (analog) : 5 analog blocks can be disabled independently.
ymf715e may 21, 1998 -23- 8-1. partial power down mode functional blocks comprising opl3-sa3 which are shown in fig.8-1, are designed so they can be disabled independent of each other. sa3 control register, index 12h and 13h, implements these controls (see section 9-1-5). , blocks in the above diagram show those that can be disabled/enabled. note, however, the opl3-sa3 dissipates more power with all these blocks partial power downed than that can be achieved in power save mode 2. in this mode, master volume is not muted, so all analog input sources and enabled digital sources (i.e. fm, sb, wss etc.) can be heard. note : aux2 inputs are exceptions in this regard since setting fm-dac at index 13h of sa3 control register inhibits the inputs altogether. 8-2. power save mode sa3 control register, index 01h, psv and pdx bits, implement these controls. clock generator can be controlled under either two options. (i) power save mode 1 (clock generator control : disabled (stop)) (psv=pdx=1) it is necessary to take some time before clock oscillation to stabilize. power dissipation of digital portion becomes about 100ua(typ.), and that of analog portion becomes about 5ma(typ.). (ii) power save mode 2 (clock generator control : enabled (crystals keep on oscillating)) (psv=1, pdx=0) leaving power save mode gets the opl3-sa3 back into function instantly. power dissipation of digital portion becomes about 10ma(typ.), and that of analog portion becomes about 5ma(typ.). in these power save modes, the outl/r pins will keep the vref voltage. during these modes, master volume is automatically muted, so all audio sources can not heard. after resuming from these modes, master volume is still muted. 8-3. global power down mode (pdn=pdx=1) this mode is to minimize power dissipation by stopping all the function of opl3-sa3. it is necessary to take some time before clock oscillation to stabilize. total dissipation becomes about 10ua(typ.). vref voltage slowly decays to ground on transition into this mode, and quickly returns to vref on transition from this mode. during this mode, master volume is automatically muted, so all audio sources can not heard. after resuming from this mode, master volume is still muted.
ymf715e may 21, 1998 -24- 8-4. suspend/resume mode there is no read only or hidden state registers in opl3-sa3. this means you can always read and save these values before power off and can set those values back in registers after reset or power on to achieve the suspend/resume capability. correspondence to apm note : analog power off feature opl3-sa3 has the special feature that the analog power supplies can be removed from opl3-sa3. this feature is independent of digital portion. apm opl3-sa3 win(driver) bios on on oo apm enabled partial power down ox apm standby power save(down) oo apm suspend off oo off off oo
ymf715e may 21, 1998 -25- 9. register description 9-1. sa sound system 9-1-1. opl3 listed below are the opl3-l register for adlib compatibility. adlib base (r) status register port adlib base (w) address port for register array 0 adlib base + 1 (r/w) data port adlib base + 2 (w) address port for register array 1 adlib base + 3 (r/w) data port wavetable upgrade (opl4-ml/ml2) is available by setting /exten (sel=3, 4, 7) to l. and, additional i/o ports listed below can also be accessed. in case of sb mode, adlib base + 2, 3 is write only registers. adlib base + 4 (r) status port for wavetable register adlib base + 4 (w) address port for wavetable register adlib base + 5 (r/w) data port wavetable register adlib base + 6 (r/w) command port for midi processor adlib base + 7 (r) status port for midi processor adlib base + 7 (w) control port for midi processor opl3 status register (ro): index d7 d6 d5 d4 d3 d2 d1 d0 xxh irq ft1 ft2 - - busy - busy opl3 data register array 0 (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 00 - 01h lsi test 02h timer 1 03h timer 2 04h rst mt1 mt2 - - - st2 st1 08h - nts - - - - - - 20 - 35h am vib egt ksr mult 40 - 55h ksl tl 60 - 75h ar dr 80 - 95h sl rr a0 - a8h f-num (l) b0 - b8h - - kon block f-num (h) bdh dam dvb rhy bd sd tom tc hh c0 - c8h * * chr chl fb cnt e0 - f5h----- ws
ymf715e may 21, 1998 -26- opl3 data register array 1 (r/w) index d7 d6 d5 d4 d3 d2 d1 d0 00 - 01h lsi test 04h - - connection sel 05h-----new3*new 20 - 35h am vib egt ksr mult 40 - 55h ksl tl 60 - 75h ar dr 80 - 95h sl rr a0 - a8h f-num (l) b0 - b8h - - kon block f-num (h) c0 - c8h * * chr chl fb cnt e0 - f5h----- ws the bit remarked * indicates that these can be read and written but not effective. note : the wait time of 960ns(min.) is needed before access to opl3 registers. 9-1-2. sound blaster pro compatibility the followings are the i/os for sound blaster pro compatibility. sb base (r) opl3 status port sb base (w) opl3 address port for register array 0 sb base + 1h (r/w) opl3 data register sb base + 2h (w) opl3 address port for register array 1 sb base + 3h (r/w) opl3 data port sb base + 4h (w) sb mixer address port sb base + 5h (r/w) sb mixer data port sb base + 6h (w) dsp reset port sb base + 8h (r) opl3 status port sb base + 8h (w) opl3 address port for register array 0 sb base + 9h (r/w) opl3 data port sb base + ah (r) dsp read data port sb base + ch (r) dsp write-buffer status port sb base + ch (w) dsp write command/data port sb base + eh (r) dsp read-buffer status port
ymf715e may 21, 1998 -27- 9-1-2-1. dsp command listed below are the supported commands of dsp defined sound blaster pro compatibility. cmd support function 10h o 8bit direct mode digitized sound i/o output 14h o 8bit single-cycle dma mode digitized sound output 16h *1 8bit to 2bit adpcm single-cycle dma mode digitized sound output 17h *1 8bit to 2bit adpcm single-cycle dma mode digitized sound output with ref. byte 1ch o 8bit auto-init dma mode digitized sound output 1fh *1 8bit to 2bit adpcm auto-init dma mode digitized sound output with ref. byte 20h *1 8bit direct mode single byte digitized sound input 24h *1 8bit single-cycle dma mode digitized sound input 2ch *1 8bit auto-init dma mode digitized sound input 30h o polling mode midi input 31h o interrupt mode midi input 34h o uart polling mode midi i/o 35h o uart interrupt mode midi i/o 36h o(*2) uart polling mode midi i/o with time stamping 37h o(*2) uart interrupt mode midi i/o with time stamping 38h o midi output 40h o set digitized sound transfer time constant 48h o set dsp block transfer size 74h o 8bit to 4bit adpcm single-cycle dma mode digitized sound output 75h o 8bit to 4bit adpcm single-cycle dma mode digitized sound output with ref. byte 76h *1 8bit to 3bit adpcm single-cycle dam mode digitized sound output 77h *1 8bit to 3bit adpcm single-cycle dma mode digitized sound output with ref. byte 7dh o 8bit to 4bit adpcm auto-init dma mode digitized sound output with ref. byte 7fh *1 8bit to 3bit adpcm auto-init dma mode digitized sound output with ref. byte 80h o pause dac for a duration 90h o 8bit high-speed auto-init dma mode digitized sound output 91h o 8bit high-speed single-cycle dma mode digitized sound output 98h *1 8bit high-speed auto-init dma mode digitized sound input 99h *1 8bit high-speed single-cycle dma mode digitized sound input a0h *1 set input mode to mono a8h *1 set input mode to stereo d0h o pause 8bit dma mode digitized sound i/o d1h *1 turn on speaker d3h *1 turn off speaker d4h o continue 8bit dma mode digitized sound i/o d8h *1 get speaker status dah o exit 8bit auto-init dma mode digitized sound i/o e1h o get dsp version number note : *1) these commands are performed in state-machine, but they are not effective. *2) midi data can not be received. additional undocumented commands are included.
ymf715e may 21, 1998 -28- 9-1-2-2. sound blaster pro compatibility mixer the table below is the register map of mixer of sound blaster pro compatibility. index d7 d6 d5 d4 d3 d2 d1 d0 00h reset mixer 04h voice vol. lch - voice vol. rch 0ah----- mic vol. - 0ch - - input filter - low pass filter input source - 0eh - - output filter --- stereo sw - 22h master vol. lch - master vol. r - 26h midi vol. lch - midi vol. rch - 28h cd vol. lch - cd vol. rch - 2eh line vol. lch - line vol. rch - the bit remarked indicates that these can be read and written but not effective. the actual value written to the master vol., midi vol., cd vol. and line vol. is based on the table shown below. and when read, actual value cannot be read and written value to each register is read instead. voice vol. (04h), cd vol. (28h), line vol. (2eh) 01234567 0 mute mute mute mute mute mute mute mute 1 mute -28.5db -22.5db -16.5db -10.5db -7.5db -3.0db 0db 2 mute -22.5db -16.5db -10.5db -7.5db -3.0db 0db 0db 3 mute -16.5db -10.5db -7.5db -3.0db 0db 0db 0db 4 mute -10.5db -7.5db -3.0db 0db 0db 0db 0db 5 mute -7.5db -3.0db 0db 0db 0db 0db 0db 6 mute -3.0db 0db 0db 0db 0db 0db 0db master volume (22h) 7 mute 0db 0db 0db 0db 0db 0db 0db
ymf715e may 21, 1998 -29- midi vol. (26h) 0123456 7 0 mute mute mute mute mute mute mute mute 1 mute -24.0db -18.0db -12.0db -6.0db -3.0db +1.5db +4.5db 2 mute -18.0db -12.0db -6.0db -3.0db +1.5db +4.5db +4.5db 3 mute -12.0db -6.0db -3.0db +1.5db +4.5db +4.5db +4.5db 4 mute -6.0db -3.0db +1.5db +4.5db +4.5db +4.5db +4.5db 5 mute -3.0db +1.5db +4.5db +4.5db +4.5db +4.5db +4.5db 6 mute +1.5db +4.5db +4.5db +4.5db +4.5db +4.5db +4.5db master volume (22h) 7 mute +4.5db +4.5db +4.5db +4.5db +4.5db +4.5db +4.5db mixer register sb mixer wss mixer midi vol. ? aux2 vol. cd vol. ? aux1 vol. line vol. ? line vol. default sb mixer master vol. = (99h) midi vol. = +4.5db (99h) voice vol. = 0db (99h) cd vol. = mute (11h) line vol. = mute (11h) wss mixer aux2 vol. = +4.5db (05h) aux1 vol. = mute (88h) voice vol. = mute (80h) line vol. = mute (88h) mono vol. = mute(min, mout) (c0h) sa3 ctrl master vol. = -14db (07h) mic vol. = mute (88h)
ymf715e may 21, 1998 -30- 9-1-3. wss compatible 16-bit codec the followings are the i/os for window sound system compatibility. wss base (r) wss configuration register port wss base + 3h (r) wss status register port wss base + 4h (r/w) wss codec index address port wss base + 5h (r/w) wss codec index data port wss base + 6h (r/w) wss codec status port wss base + 7h (r/w) wss codec pio data port wss configuration register (ro): portd7d6d5d4d3d2d1d0 +0h 0 0 irq dma this register is used to indicate what resources is assigned and it is read only register. irq: 0: no interrupt channel is available 1: irq7 is available 2: irq9 is available 3: irq10 is available 4: irq11 is available 5-7: reserved. dma: 0: no dma channel is available 1: dma0 2: dma1 3: dma3 4-7: reserved notice) in the case that codec is in dual dma mode, only playback dma channels are valid and recording dma channels are ignored. wss status register (ro): portd7d6d5d4d3d2d1d0 +03h sbhc 0 04h wss codec direct registers (r/w): portd7d6d5d4d3d2d1d0 +4h init mce trd index address +5h index data +6h cu/l cl/r crdy ser pu/l p/r prdy int +7h pio data
ymf715e may 21, 1998 -31- wss codec indirect registers (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 00h lss1 lss0 lmge - lig3 lig2 lig1 lig0 01h rss1 rss0 rmge - rig3 rig2 rig1 rig0 02h lx1m - - lx1g4 lx1g3 lx1g2 lx1g1 lx1g0 03h rx1m - - rx1g4 rx1g3 rx1g2 rx1g1 rx1g0 04h lx2m - - lx2g4 lx2g3 lx2g2 lx2g1 lx2g0 05h rx2m - - rx2g4 rx2g3 rx2g2 rx2g1 rx2g0 06h lom - loa5 loa4 loa3 loa2 loa1 loa0 07h rom - roa5 roa4 roa3 roa2 roa1 roa0 08h fm1 fm0 c/l s/m cfs2 cfs1 cfs0 csl 09h cpio ppio - - acal sdc cen pen 0ah xtl1* xtl0* - - - - ien - 0bh cor pur aci drs 0 0 0 0 0ch mid mode - - id3 id2 id1 id0 0dh lba5 lba4 lba3 lba2 lba1 lba0 - lbe 0eh pub7 pub6 pub5 pub4 pub3 pub2 pub1 pub0 0fh plb7 plb6 plb5 plb4 plb3 plb2 plb1 plb0 10h olb te cmce pmce - - - dacz 11h-------hpf* 12h llm - - llg4 llg3 llg2 llg1 llg0 13h rlm - - rlg4 rlg3 rlg2 rlg1 rlg0 14h tl7 tl6 tl5 tl4 tl3 tl2 tl1 tl0 15h tu7 tu6 tu5 tu4 tu3 tu2 tu1 tu0 16h-------- 17h-------- 18h - ti ci pi cu co po pu 19h v2 v1 v0 - - cid2 cid1 cid0 1ah mim - - - mia3 mia2 mia1 mia0 1bh-------- 1ch fmt1 fmt0 c/l s/m - - - - 1dh-------- 1eh cub7 cub6 cub5 cub4 cub3 cub2 cub1 cub0 1fh clb7 clb6 clb5 clb4 clb3 clb2 clb1 clb0 the bit remarked * indicates that these can be read and written but not effective.
ymf715e may 21, 1998 -32- mixer default: 02h:aux1l = 88h (mute) 03h:aux1r = 88h (mute) 04h:aux2l = 05h (+4.5db) 05h:aux2r = 05h (+4.5db) 06h:dacl = 80h (mute) 07h:dacr = 80h (mute) 12h:linel = 88h (mute) 13h:liner = 88h (mute) 1ah:monoin = c0h (mute) 9-1-4. mpu401 the followings are the i/os for mpu401 compatibility. mpu base (r/w) midi data port mpu base +1 (r) status register port mpu base + 1 (w) command register port 9-1-5. opl3-sa3 control register this register is used to control the additional functions (ex. power management, wide stereo). ctrl base (r/w) index port ctrl base +1 (r/w) data port power management (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 01h 0 0 adown 0 0 psv pdn pdx adown (analog down)... analog power supplies can be removed from opl3-sa3, if adown=1. set this bit to 0, before analog power is supplied again. psv (power save)... setting this bit to 1 makes opl3-sa3 in power save mode that is categorized into two types. power save mode 1 where psv=pdx=1, clock oscillation is disabled and power dissipation of digital portion becomes about 100ua(typ.), and that of analog portion becomes about 5ma(typ.). power save mode 2 where psv=1 and pdx=0, clock oscillation is active. however power dissipation of digital portion becomes about 10ma(typ.), and that of analog portion becomes about 5ma(typ.). pdn (power down)... setting this bit to 1 makes in power down mode. pdx (oscillation stop)... setting this bit to 1 makes the clock oscillation halt. default : 00h
ymf715e may 21, 1998 -33- notice) 1) set d7, d6, d4 and d3 bits to 0. 2) in the power save modes 1, 2, the outl/r pins will keep the vref voltage. in the power down mode, vref voltage slowly decays to ground on transition into this mode, and quickly returns to vref on transition from this mode. during these modes (power save/down), master volume is automatically muted, so all audio sources cannot be heard. after resuming these modes, master volume is still muted. system control (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 02h sbhe - ymode1 ymode0 - idsel1 idsel0 vze sbhe... when at-bus is used, set to 0 and set to 1 in case of xt-bus. ymode1-0... 3d enhancement mode according to the application can be selected by these two bits as follows. ymode1 ymode0 3d enhancement mode 0 0 desktop mode 0 1 notebook pc mode (1) 1 0 notebook pc mode (2) 1 1 hi-fi mode idsel1, idsel0... these two bits specify the dsp version of sound blaster compatible portion. the different return value of dsp command e1h (get dsp version number) of sound blaster pro is got by these bits in. 1st byte 2nd byte idsel1 idsel0 (major ver) (minor ver) 0 0 03h 01h 0 1 02h 01h 1 0 01h 05h 1 1 00h 00h vze... i 2 s audio format can be fed to bclk_zv, lrck_zv, sin_zv pins of opl3-sa3 by setting this bit to 1 regardless of the /exten, when zoomed video port is in use. default : 00h notice) input signals, bclk_zv and lrck_zv pins which appear on sel=4 or 5 mode, should be oscillated, when vze=1.
ymf715e may 21, 1998 -34- interrupt channel configuration (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 irq-b irq-a 03h opl3 mpu sb wss opl3 mpu sb wss there are four devices (wss (windows sound system codec), sb (sound blaster compatible portion), opl3, mpu (mpu401)) that can be an interrupt source. this register specifies what interrupt source is routed to two physical interrupt (irqa and irqb) of opl3-sa3. the device written to 1 is assigned to the corresponding interrupt. and by writing all 1 to upper or lower half byte, it is possible to share all interrupt sources to a single physical interrupt line. default : 69h irq-a: wss + opl3 irq-b: sb + mpu401 notice) do not assign a device to both irqa and irqb. interrupt (irq-a) status (ro): index d7 d6 d5 d4 d3 d2 d1 d0 04h - mv opl3 mpu sb ti ci pi this register is the status register that indicates which is the interrupt source of irqa. when an interrupt occurs, the corresponding bit becomes 1 and its flag (except mv bit) is cleared when the interrupt routine is completed. this register is not cleared by writing to this register. mv... hardware volume interrupt flag : if configured ven=1(index 0ah, d7 bit), the interrupt occurs when either /volup or /voldw is low level or when both are low level to request mute. the interrupt will be posted in the irq-a channel, if irq-a mv=1 (index 17h, d4 bit). note that when the muting is in effect, the subsequent mute requests which does not change any register contents will generate interrrupts. the ignored up/down requests (up requests with 0db volume attn., down requests with -30db) will not generate interrupts. this bit is cleared upon host's reading the master volume lch register at index 07h. opl3... internal fm-synthesizer timer flag : note that this flag will become undefined for the configurations (sel=3,4,7) using external synthesizer (i.e. opl4-ml/ml2). mpu... mpu401 interrupt flag sb... sound blaster compatible playback interrupt flag ti... timer flag of codec ci... recording flag of codec pi... playback flag of codec
ymf715e may 21, 1998 -35- interrupt (irq-b) status (ro): index d7 d6 d5 d4 d3 d2 d1 d0 05h - mv opl3 mpu sb ti ci pi this register is the status register that indicates which is the interrupt source of irqb. when an interrupt occurs, the corresponding bit becomes 1 and its flag (except mv bit) is cleared when the interrupt routine is completed. this register is not cleared by writing to this register. mv... hardware volume interrupt flag : if configured ven=1(index 0ah, d7 bit), the interrupt occurs when either /volup or /voldw is low level or when both are low level to request mute. the interrupt will be posted in the irq-b channel, if irq-b mv=1 (index 17h, d5 bit). note that when the muting is in effect, the subsequent mute requests which does not change any register contents will generate interrrupts. the ignored up/down requests (up requests with 0db volume attn., down requests with -30db) will not generate interrupts. this bit is cleared upon host's reading the master volume lch register at index 07h. opl3... internal fm-synthesizer timer flag : note that this flag will become undefined for the configurations (sel=3,4,7) using external synthesizer (i.e. opl4-ml/ml2). mpu... mpu401 interrupt flag sb... sound blaster compatible playback interrupt flag ti... timer flag of codec ci... recording flag of codec pi... playback flag of codec dma configuration (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 dma-b dma-a 06h - sb wss-r wss-p - sb wss-r wss-p there are three devices (wss-p (windows sound system codec playback), wss-r (windows sound system codec recording) , sb(sound blaster compatible playback)) that may use a dma channel. however 2 dma channels (dmaa and dmab) are available at maximum, this register specifies which device is routed to the physical dma channels. and the device written to 1 is assigned to the corresponding dma channel. default : 61h dma-a: wss-p dma-b: wss-r + sb notice) do not assign a device to both dma-a and dma-b.
ymf715e may 21, 1998 -36- master volume lch (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 07h mvlm - - - mvl3 mvl2 mvl1 mvl0 this register specifies the master volume of left channel. mvlm... setting to 1 to this bit makes master volume left channel muted. mvl3-0... these bits determine the attenuation level of master volume left channel by -2db step. when all bits are set to 0, volume is maximum (0db) and when all bits are set to 1, volume is minimum (-30db). default : 07h (-14db) notice) during the power on reset and power down/save mode, master volume is automatically muted, so all audio sources can not be heard. in resuming from power down/save mode, it is still muted. master volume rch (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 08h mvrm - - - mvr3 mvr2 mvr1 mvr0 this register specifies the master volume of right channel. mvrm... setting to 1 to this bit makes master volume right channel muted. mvr3-0... these bits determine the attenuation level of master volume right channel by -2db step. when all bits are set to 0, volume is maximum (0db) and when all bits are set to 1, volume is minimum (-30db). default : 07h (-14db) notice) during the power on reset and power down/save mode, master volume is automatically muted, so all audio sources can not be heard. in resuming from power down/save mode, it is still muted. mic volume (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 09h micm - - mcv4 mcv3 mcv2 mcv1 mcv0 this register specifies the master volume of mic. micm... setting to 1 to this bit makes mic volume muted. mcv4-0... these bits determine the gain level of mic volume by -1.5db step. when all bits are set to 0, volume is maximum(+12db) and when all bits are set to 1, volume is minimum (-34.5db). default : 88h
ymf715e may 21, 1998 -37- miscellaneous: index d7 d6 d5 d4 d3 d2 d1 d0 0ah ven - - mcsw mode ver2 ver1 ver0 ven... this bit enables the hardware volume control. default is ven=1. mcsw... this bit determines whether rch of mic input or loopback of monaural output is connected to a/d. this will be useful to support the echo cancellation. when 0 is set to this bit, rch of mic input is selected. mode... this bit indicates the sb or wss mode. if mode=0, it is the sb mode. this bit is read only. ver2-0... these bits indicate the version of opl3-sa3 and read only (ver2=1, ver1=0, ver0=0). default : 84h wss dma base counter (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 0bh playback base counter (low) 0ch playback base counter (high) 0dh recording base counter (low) 0eh recording base counter (high) these registers are to load the value to wss dma base counter and read out the present value. initial value is ffh. in case of loading the value, both high and low bytes are loaded to internal dma counter when the high byte is written. the value set to this register is (the number of transfer byte) -1 that is same as wss codec indirect register 0eh, 0fh, 1eh and 1fh. when read these registers, the present value of dma base counter is read out. these registers are used mainly to support the suspend/resume feature that is very important for notebook pc application. wss interrupt scan out/in (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 0fh-----stiscispi use the bits in this register to set wss interrupt-flags(wss codec indirect register, index 18h, d6-d4 bits). sti... 1 in this bit means ti=1 and corresponding irq active. sci... 1 in this bit means ci=1 and corresponding irq active. spi... 1 in this bit means pi=1 and corresponding irq active. default : 00h notice) to make irq active, it is necessary to set 1 to wss codec indirect register index 0ah ien bit.
ymf715e may 21, 1998 -38- sound blaster compatibility internal state scan out/in (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 10h sbpda - - - ss sm se sbpdr sbpda... sound blaster power down acknowledgment: 1 in sbpda acknowledges that opl3-sa3 is ready for scanning internal state data in/out or for power down operation. this flag is read-only. ss... scan select : set 1 in this bit when reading or writing internal state. set 0 for normal operation. sm... scan mode : setting 1 in this bit means the internal states are read(out). set 0 for write(in). se... scan enable : 1 to 0 transition in this bit clocks the shifting internal state scan data out 1-bit at a time. sbpdr... sound blaster power down request : 1 in this bit inhibits further dma requests and have the internal state begin shutdown procedure. 1 in sbpda signals the shutdown procedure completion. default : 00h sound blaster compatibility internal state scan data (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 11h scan data scan data... data port for internal state scan data in/out. default : 00h notice) the sound blaster compatibility internal state scan out/in sequence are shown in the following fig.9-1.
ymf715e may 21, 1998 -39- i) scan out sbpda=0 sbpdr=1 sbpda=1 sm=1 ss=1 se=1 ? 0 : not ready for scanning internal state data : inhibit further dma, internal state shutdown : ready for scanning internal state data : internal state read out : reading internal state : shifting internal state scan data out 1-bit at a time 8 times n times : internal state scan data out scan data (read) suspend prepareration n=29 byte (total scan data=228 bit (28 byte 8+4bit)) fig. 9-1 sound blaster compatibility internal state scan out/in sequence ii) scan in sbpda=0 sbpdr=1 sbpda=1 sm=0 ss=1 se=1 ? 0 : not ready for scanning internal state data : inhibit further dma, internal state shutdown : ready for scanning internal state data : internal state write in : writing internal state : shifting internal state scan data in 1-bit at a time 8 times n times : internal state scan data in scan data (write) resume completion sm=0 ss=0 sbpdr=0
ymf715e may 21, 1998 -40- digital block partial power down (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 12h joy mpu mclko fm wss_r wss_p sb pnp this register specifies the partial power management of the digital portion. this function is to spare power dissipation in unneeded blocks. joy... setting this bit to 1 makes the joystick portion in power down mode. mpu... setting this bit to 1 makes the mpu401 portion in power down mode. mclko when set to 1, master clock(33.8688mhz) is disable, which appears on the pin mp9(sel=1,3,4,7). when set to 0, normal operation is active. fm... setting this bit to 1 makes the internal fm(opl3) portion in power down mode. wss_r... setting this bit to 1 makes the wss recording portion in power down mode. wss_p... setting this bit to 1 makes the wss playback portion and the digital loopback portion in power down mode. sb... setting this bit to 1 makes the sound blaster compatible portion in power down mode. pnp... setting this bit to 1 makes the pnp portion in power down mode. default : 00h analog block partial power down (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 13h - - - fmdac a/d d/a sbdac wide this register specifies the partial power management of the analog portion. the respective outputs of the blocks which are to be disabled should be muted beforehand. fmdac... setting this bit to 1 makes the fmdac portion for the internal fm(opl3) or external synthesizer(opl4-ml/ml2) or zv port etc. in power down mode. aux2 should be muted via register before setting the fmdac portion to power down. a/d... setting this bit to 1 makes the a/d portion for the wss recording in power down mode. d/a... setting this bit to 1 makes the d/a portion for the wss playback in power down mode. wss codec indirect register, index 06h and 07h, lom and rom bits must be 1, before doing this. sbdac... setting this bit to 1 makes the sbdac portion in power down mode. sb master volume should be muted via register before setting the sbdac portion to power down. wide... setting this bit to 1 makes the wide stereo(3d enhanced control) portion in power down mode. the 3d enhanced parameter registers at index 14, 15, and 16h must be 00h, when doing this. default : 00h notice) in the partial power down mode, master volume is not muted, so all analog input sources and enabled digital sources (i.e. fm, sb, wss etc.) can be heard. note that aux2 inputs are exceptions in this regard since setting fmdac bit inhibits the inputs altogether.
ymf715e may 21, 1998 -41- 3d enhanced control(wide) (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 14h - wider2 wider1 wider0 - widel2 widel1 widel0 this register specifies the wide level of the 3d enhanced control. wider2-0... these bits determine the wide level of 3d enhanced control on right channel by 8 step (if wider2-0=0, 0%, and wider2-0=7, 100%). widel2-0... these bits determine the wide level of 3d enhanced control on left channel by 8 step (if widel2-0=0, 0%, and widel2-0=7, 100%). default:00h 3d enhanced control(bass) (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 15h - bassr2 bassr1 bassr0 - bassl2 bassl1 bassl0 this register specifies the bass level of the 3d enhanced control. bassr2-0... these bits determine the bass level of 3d enhanced control on right channel by 1.5db step(max. 10.5db). bassl2-0... these bits determine the bass level of 3d enhanced control on left channel by 1.5db step(max. 10.5db). default : 00h 3d enhanced control(treble) (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 16h - trer2 trer1 trer0 - trel2 trel1 trel0 this register specifies the treble level of the 3d enhanced control. trer2-0... these bits determine the treble level of 3d enhanced control on right channel by 1.5db step(max. 10.5db). trel2-0... these bits determine the treble level of 3d enhanced control on left channel by 1.5db step(max. 10.5db). default : 00h notice) the 3d enhanced control parameter registers at index 14h, 15h and 16h must be 00h, when doing the wide stereo portion in power down mode (setting sa3 control register, index 13h, wide bit to 1). hardware volume interrupt channel configuration (r/w): index d7 d6 d5 d4 d3 d2 d1 d0 17h - - irq-b mv irq-a mv -*** the hardware volume can source interrupt. this register indicates which interrupt channel will be used. if irq-a mv=1, assigned to irq-a. default : 00h notice) writing to the other bit positions is invalid, though the bits remarked * (d2-d0) will retain written values. d3, d6 and d7 will always returns 0 when read.
ymf715e may 21, 1998 -42- multi-purpose select pin status (ro): index d7 d6 d5 d4 d3 d2 d1 d0 18h 1 sel2 sel1 sel0 - - - 0 this is a status register that indicates the state of multi-purpose pin. sel2-0... the state of sel2-0 pins is reflected to these bits. the multi-purpose function of ymf715e (opl3-sa3) can be confirmed by reading the bits. these bits are read only. default : (1xxx0000) b 9-2. joystick port d7 d6 d5 d4 d3 d2 d1 d0 xxh jbb2 jbb1 jab2 jab1 jbcy jbcx jacy jacx jacx... joystick a, coordinate x jacy... joystick a, coordinate y jbcx... joystick b, coordinate x jbcy... joystick b, coordinate y jab1... joystick a, button 1 jab2... joystick a, button 2 jbb1... joystick b, button 1 jbb2... joystick b, button 2 9-3. modem the following pins are for modem interface with pnp supported. /mcs... chip select (eight consecutive byte i/o) mirq... interrupt signal and min is the analog input to mix the telephone line. min... analog input 9-4. cd-rom the following pins are for ide cd-rom interface with pnp supported. /cdcs0... chip select for cd-rom /cdcs1... chip select for cd-rom cdirq... interrupt signal other signals needed for cd-rom must be generated by the external pals, which is described in section 1-3.
ymf715e may 21, 1998 -43- electrical characteristics absolute maximum ratings note : v dd =dv dd =av dd , v ss =dv ss =av ss =0[v] recommended operating conditions note : dv ss =av ss =0[v] dc characteristics 1 (dv dd = 5.0 0.25[v]) item symbol minimum maximum unit power supply voltage (analog/digital) v dd v ss -0.5 v ss +7.0 v input voltage v in v ss -0.5 v dd +0.5 v output voltage v out v ss -0.3 v dd +0.3 v input current i in -20 20 ma storage temperature t stg -50 125 c item symbol min. typ. max. unit power supply 1 (analog) av dd 4.75 5.00 5.25 v 5.0v spec. (digital) dv dd 4.75 5.00 5.25 v power supply 2 (analog) av dd 4.75 5.00 5.25 v 3.3v spec. (digital) dv dd 3.00 3.30 3.60 v operating ambient temperature t op 02570 c item symbol condition min. typ. max. unit ttl-input pins high level input voltage 1 v ih1 except 2.0 v low level input voltage 1 v il1 schmitt inputs 0.8 v cmos-input pins high level input voltage 2 v ih2 0.7dv dd v low level input voltage 2 v il2 0.2dv dd v schmitt vt- (h to l) v t -0.81.5v schmitt vt+ (l to h) v t +1.32.1v schmitt hysteresis v h1 *1 0.3 v v h2 *2 0.1 v input leakage current i l v in =dv ss , dv dd -10 10 m a input capacitance c i 10 pf r u1 rxd 20 50 100 k w pull up register r u2 gp7 ~ 4 30 100 200 k w r u3 otherwise 50 200 400 k w ttl-output pins high level output voltage 1 v oh1 2.4 v low level output voltage 1 v ol1 *3 0.4(0.5) v ttl output current i ohl1 d7 ~ 0 pins *3 16(24) ma i ohl2 irqn, drqn pins *3 8(12) ma i ohl3 txd pin 4 ma i ohl4 mp9 ~ 0 pins 2 ma
ymf715e may 21, 1998 -44- note : dv ss =av ss =0[v], t op =0~70 c, av dd =5.0[v] *1 : applicable to s chmitt input pins without /volup, /voldw. *2 : applicable to /volup and /voldw pins. *3 : when v ol1 =max. 0.5v, the value into the brackets is specified at i ohl1, 2 . dc characteristics 2 (dv dd = 3.3 0.30[v]) note : dv ss =av ss =0[v], t op =0~70 c, av dd =5.0[v] the specifications marked * are different from the value at dv dd = 5.0 0.25[v]. item symbol condition min. typ. max. unit cmos output pins high level output voltage 2 v oh2 i oh =2ma 0.8dv dd v low level output voltage 2 v ol2 i ol =2ma 0.4 v output leakage current o l hi_z:v in =dv ss , dv dd -10 10 m a output capacitance c o 10 pf item symbol condition min. typ. max. unit ttl-input pins high level input voltage 1 v ih1 except 2.0 v low level input voltage 1 v il1 schmitt inputs 0.8 v cmos-input pins high level input voltage 2 v ih2 0.7dv dd v low level input voltage 2 v il2 0.2dv dd v schmitt vt- (h to l) v t -0.81.5v schmitt vt+ (l to h) v t + 1.3 2.2 * v schmitt hysteresis v h 0.3 * v input leakage current i l v in =dv ss , dv dd -10 10 m a input capacitance c i 10 pf r u1 rxd 20 50 100 k w pull up register r u2 gp7 ~ 4 30 100 200 k w r u3 otherwise 50 200 400 k w ttl-output pins high level output voltage 1 v oh1 2.4 v low level output voltage 1 v ol1 0.4 v ttl output current i ohl1 d7 ~ 0 pins 2 * ma i ohl2 irqn, drqn pins 2 * ma i ohl3 txd pin 2 * ma i ohl4 mp9 ~ 0 pins 2 ma cmos output pins high level output voltage 2 v oh2 i oh =2ma 0.8dv dd v low level output voltage 2 v ol2 i ol =2ma 0.4 v output leakage current o l hi_z:v in =dv ss , dv dd -10 10 m a output capacitance c o 10 pf
ymf715e may 21, 1998 -45- ac characteristics cpu interface & dma bus cycle :fig.1,2,3,4,5,6,7,8 note : dv ss =av ss =0[v], t op =0~70 c, dv dd =5.0 0.25[v] or 3.3 0.30[v], av dd =5.0[v] *... the value into the brackets is specified at dv dd =3.3 0.30[v]. serial audio (zoomed video) interface input :fig.9 note : dv ss =av ss =0[v], t op =0~70 c, dv dd =5.0 0.25[v] or 3.3 0.30[v], av dd =5.0[v] duty search point is 1/2 dv dd . item symbol min. typ. max. unit /dack inactive to /iow, /ior falling edge t aks 50 ns /dack active from /iow, /ior rising edge t akh 10 ns address set up to /iow, /ior active t as 40 ns address hold to /iow, /ior inactive t ah 10 ns /iow write pulse width t ww 90 ns write data set up to /iow active t wds 20 ns write data hold to /iow inactive t wdh 10 ns /ior read pulse width t rw 90 ns read data access time t acc 80 ns read data hold from /ior inactive t rdh 0ns drq hold from /iow, /ior falling edge t dgh 020ns /dack set up to /iow, /ior falling edge t sf 25 ns /dack hold to /iow, /ior rising edge t hr 25 ns time between rising edge of /iow, /ior to next falling edge of /iow, /ior t nx 100 ns valid address from /syncs or /mcs or /cdcs1-0 t ex1 70(90) * ns /syncs or /mcs or /cdcs1-0 hold to valid address t ex2 70(90) * ns reset pulse width t rst 90 m s item symbol condition min. typ. max. unit bclk cycle f bck 32fs 48fs 64fs khz bclk duty d bclk 40 50 60 % lrck hold time t lrh bclk - /lrck -120 120 ns sin set up time t ds bclk - /sin 20 ns sin hold time t dh bclk - /sin 20 ns clko frequency f clko33 33.8688 mhz clko duty d clko33 f 33 =50% 40 50 60 %
ymf715e may 21, 1998 -46- miscellaneous note : dv ss =av ss =0[v], t op =0~70 c duty search point is 1/2 dv dd . *... dv dd = 5.0 0.25[v] or 3.3 0.30[v], av dd = 5.0 0.25[v] power save1 : sa3 control register, index 01h, psv=pdx=1 power save2 : sa3 control register, index 01h, psv=1, pdx=0 partial power down : sa3 control register, index 12h=ffh, index 13h=1fh power down : sa3 control register, index 01h, pdn=pdx=1 item symbol condition min. typ. max. unit master clock frequency f 33 * 33.8688 mhz (xtal 33) duty d f33 40 50 60 % master clock frequency f 24 * 24.5760 mhz (xtal 24) duty d f24 40 50 60 % power consumption 1 p op1 dv dd =5.0 0.25[v] 40 50 ma (normal) av dd =5.0 0.25[v] 50 60 ma p op2 dv dd =3.3 0.30[v] 25 35 ma power consumption 2 dv dd =5.0 0.25[v] 100 m a (power save 1) av dd =5.0 0.25[v] 5ma dv dd =3.3 0.30[v] 80 m a power consumption 3 dv dd =5.0 0.25[v] 10 ma (power save 2) av dd =5.0 0.25[v] 5ma dv dd =3.3 0.30[v] 7ma power consumption 4 dv dd =5.0 0.25[v] 20 ma (partial power down) av dd =5.0 0.25[v] 15 ma dv dd =3.3 0.30[v] 10 ma power consumption 5 dv dd =5.0 0.25[v] 10 40 m a (power down) av dd =5.0 0.25[v] 010 m a dv dd =3.3 0.30[v] 10 30 m a
ymf715e may 21, 1998 -47- fig.2 i/o read cycle valid valid d7-0 /dack3,1,0 (a15-12) a11-0 /ior t akh t aks t rdh t acc t rw t ah t as fig.1 i/o write cycle valid d7-0 /dack3,1,0 (a15-12) a11-0 /iow t akh t aks t wdh t wds t ww t ah t as
ymf715e may 21, 1998 -48- fig.4 valid 8bit mono & adpcm dma read cycle d7-0 drq3,1,0 /dack3,1,0 /ior t dgh t rdh t acc t rw t hr t sf fig.3 8bit mono & adpcm dma write cycle d7-0 drq3,1,0 /dack3,1,0 /iow t dgh t wdh t wds t ww t hr t sf
ymf715e may 21, 1998 -49- fig.6 16bit stereo dma cycle drq3,1,0 right/low byte left/high byte d7-0 /iow,/ior /dack3,1,0 t nx left/low byte right/high byte 8bit stereo or 16bit mono dma cycle drq3,1,0 right/high byte left/low byte d7-0 /iow,/ior /dack3,1,0 t nx fig.5
ymf715e may 21, 1998 -50- serial audio interface lrck sin bclk t lrh t dh t ds 1/f bck fig.9 fig.8 t rst reset pulse width reset fig.7 external interface (external synthesizer, cd rom, modem) valid (a15-12) a11-0 /syncs or /cdcs1,0 or /mcs t ex2 t ex1
ymf715e may 21, 1998 -51- analog characteristics analog input characteristics note : dv ss =av ss =0[v], t op =25 c, dv dd =av dd =5.0[v], fs=44.1khz, 3d wide=0%, bass, treble=0db analog output characteristics note : dv ss =av ss =0[v], t op =25 c, dv dd =av dd =5.0[v], fs=44.1khz, 3d wide=0%, bass, treble=0db item condition min. typ. max. unit full scale v_input ? line/aux1,2/min/mic 2.5 2.8 3.1 vpp ? mic +20db 0.25 0.28 0.31 vpp adc resolution 16 bit recording path (adc) signal to noise ratio ? line/aux1,2/mic 78 82 db ? mic +20db 75 80 db distortion 0.05 0.1 % interchannel isolation 70 db l/r channel separation 70 db gain mismatch 0 ~ +22.5db from spec. -0.5 0.5 db frequency response 20 to 17.6khz -3.0 0.5 db input resistance 20 100 k w input capacitance 15 pf item condition min. typ. max. unit full scale line output ? olb=1 2.4 2.8 3.1 vpp ? olb=0 1.7 2.0 2.2 vpp dac resolution (wss_dac) 16 bit frequency response (wss_dac) 20 to 17.64 khz -1.0 0.5 db mix_path total signal to noise ratio ? from input (line, aux1) 85 90 db ? from input (aux2, mic) 82 87 db ? from input (mic) +20db 75 80 db ? from wss_dac 82 84 db distortion ? from input 0.003 0.02 % ? from input (mic) +20db 0.01 0.05 % ? from wss_dac 0.05 0.1 % interchannel isolation 70 db l/r channel separation 70 db gain mismatch from spec. ? +12 ~ -19.5db -0.5 0.5 db ? -21db or less -1.0 1.0 db mute attenuation -80 db vrefo voltage output 2.3 2.5 2.7 v
ymf715e may 21, 1998 -52- external dimensions the shape of the molded corner may slightly different from the shape in this diagram. the figure in the parenthesis ( ) should be used as a reference. plastic body dimensions do not include burr of resin. unit : mm note : the lsis for surface mount need especial consideration on storage and soldering conditions. for detailed information, please contact your nearest agent of yamaha. 76 100 125 75 51 50 26 16.00 0.40 14.00 0.30 14.00 0.30 16.00 0.40 0.20 0.10 or 0.18 0.10 p-0.50typ 1.70max. (installation height) 1.40 0.20 0min.(stand off) lead thickness : 0.125typ or 0.15typ (1.0) 0-10o 0.50 0.20
ymf715e may 21, 1998 -53- important notice 1. yamaha reserves the ri g ht to make chan g es to its products and to this document without notice. the information contained in this document has been carefully checked and is believed to be reliable. however, yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. these yamaha products are desi g ned only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property dama g e. use of the products in any such application is at the customer's sole risk and expense. 3. yamaha assumes no liability for incidental, consequential or special damages or injury that may result from misapplication or improper use or operation of the products. 4. yamaha makes no warranty or representation that the products are subject to intellectual property license from yamaha or anythird party, and yamaha makes no warranty or representation of non- infringement with respect to the products. yamaha specifically excludes any liability to the customer or any third party arising from or related to the products' infringement of any third party's intellectual property rights, including the patent, copyright, trademark or trade secret rights of any third party. 5. examples of use described herein are merely to indicate the characteristics and performance of yamaha products. yamaha assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. yamaha makes no warranty with respect to the products, express or implied, including, but not limited to the warranties of merchantability, fitness for a particular use and title. note) the specifications of this product are subject to improvement change without prior notice. agency yamaha corporation address inquires to : semi-conductor sales department - head office 203, matsunokijima, toyooka-mura. iwata-gun, shizuoka-ken, 438-0192 tel. +81-539-62-4918 fax. +81-539-62-5054 - tokyo office 2-17-11, takanawa, minato-ku, tokyo, 108-8568 tel. +81-3-5488-5431 fax. +81-3-5488-5088 - osaka office 1-13-17, namba naka, naniwa-ku, osaka city, osaka, 556-0011 tel. +81-6-6633-3690 fax. +81-6-6633-3691 - u.s.a. office yamaha system technology. 100 century center court, san jose, ca 95112 tel. +1-408-467-2300 fax. +1-408-437-8791

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